In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between VDD and ground. The half-rate hybrid circuit topology is implemented in 1.2 V, 65 nm CMOS. The post-layout performance including package parasitic shows that, the half-rate charge-steering hybrid has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half-rate charge-steering hybrid is 0.16mW only and energy efficiency of the hybrid is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm2.