ISICAS 2021
|
Technical Lecture and Demo
ID 7

Low-Latency Lattice-Reduction-Aided One-Bit Precoding Processor for 64-QAM 4×64 MU--MIMO Systems
Details
Presenter(s)
Yuan-Hao Huang Headshot
Yuan-Hao Huang
Affiliation
National Tsing Hua University
Country
View profile
Author(s)
Yuan-Hao Huang
Affiliation
National Tsing Hua University
View profile
Slides
  • Low-Latency Lattice-Reduction-Aided One-Bit Precoding Processor for 64-QAM 4×64 MU--MIMO Systems (application/pdf)
    Download