In this paper, we present an FPGA implementation of low latency Viterbi-Viterbi 4th Power Estimation (VV4E) based Carrier phase recovery (CPR), which mainly performs the computation in Cartesian coordinates and implements the trigonometric function with a look-up table (LUT). Evaluations on Xilinx ZCU102 show that at a frequency of 370MHz, it introduces a 22-cycle latency to handle the 29.6 GBd QPSK signals, which is the minimum value to our knowledge.