In this paper, two approximate 3×3 multipliers are proposed and the synthesis results of ASAP-7nm process library justify that they can reduce the area by 31.38\\% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2×2 multiplier to produce an 8×8 multiplier with low error-rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our best design has no DNN accuracy loss for LeNet on MNIST without the retraining. On CIFAR10, the best design has a 0.88% DNN accuracy loss on LeNet, which can be reduced to -0.2% after retraining. For larger DNNs, the DNN accuracy of the best design can achieve significant advantage over other approximate multipliers on CIFAR10.