Due to increasing the number of connected devices to IoT network, providing end-to-end security is essential. Lattice-based cryptography (LBC) is a promising method for IoT by providing reasonable security against classic and quantum attacks. Ring-BinLWE is a type of LBC that is suitable for IoT devices. However, a reliable cryptosystem should also be secure against different side-channel attacks, such as power analysis or fault injection ones. In this work, a fault resilient hardware implementation for an optimized hardware design of Binary Ring-LWE for resource-constraint IoT devices is presented. The design was implemented on the FPGA platform. The maximum frequency and occupied slices on Virtex-7 are 210.5MHz and 423, respectively. Based on the result, the proposed design occupied only 1% of the total available slices.