Limited write endurance and high write energy consumption per bit restricts the use of emerging non-volatile memory devices. Many studies concentrate on reducing the number of bit-flips per write operation to reduce the effect of bottleneck issues. In this paper, we propose a lifetime enhancement scheme for eNVM device based memories that not only distributes the number of bit-flips across the bit-stream but is also able to improve the endurance and energy performance of the NVM processors. The proposed scheme significantly reduces the number of bit-flips by ~40% in write-intensive applications and improves the processor’s performance by ~ 55%.