This paper presents the design of low-dropout (LDO) regulator optimized on power efficiency and load transient response. As the LDO is always-on block, the quiescent current is a critical parameter of LDO. The proposed circuit includes an op-amp which shows high slew rate with low quiescent current. A voltage damper circuit is included for fast load transient response. A body feedback loop helps the LDO regulator to react to relatively slow distortion of the output voltage. The proposed LDO regulator is fabricated in a 180 nm CMOS process. The test results show that maximum undershoot is 125.9 mV during load transient and 0.177 ns/μm figure-of-merit (FOM) at the quiescent current of 0.02532 mA.