In this paper, an interference-tolerant three-level synchronization scheme for wireless communication systems based on Direct Sequence Spread Spectrum (DSSS) is presented. Although the proposed synchronization scheme is demonstrated in a mixed signal IC solution, it is exportable to fully digital realizations. The proposed technique synchronizes the received pseudo-random sequence (PRS) modulated signal with the receiver (RX) reference PRS by making use of its autocorrelation properties. The proposed scheme employs 3 levels that make the proposed scheme tolerant to strong in-band interferences. Experimental results for the prototype demonstrate the capabilities of the proposed approach to achieve over 50% of clock cycle tracking even in the presence of interferences with a power of 5dB higher than the desired signal power. Fabricated in a mainstream 40nm CMOS technology, the synchronization scheme employs 100MHz PRS at TX and RX; the proposed solution consumes 18.7mW power and around 0.087mm2 silicon area.