An input folding cyclic ADC for column-parallel readout in CMOS image sensor is proposed. A double sampling circuit in the CMOS image sensor is reused to perform input folding operation in cyclic ADC. In addition, a push-pull configuration based slew rate enhancement technique is used to reduce the settling time of multiplying digital to analog converter. The ADC results in a conversion rate of 1.38~MS/s while consuming 560~$\\mu$W of power. A prototype CMOS image sensor, with 12-bit column-parallel cyclic ADC, is designed and fabricated in AMS 350~nm CMOS OPTO process at 3.3~V power supply. For a 96 $\\times$ 64 pixel array, the row readout time of 720~ns is achieved, which is two to five times smaller compared to the state-of-the-art.