This paper presents an inductor-less transmitter (TX) based on harmonic-rejection edge combiner (HREC) and delay-locked loop (DLL) to suppress the 3rd/5th harmonics. The HREC utilizing a resistance-divider technique achieves 9× frequency multiplication and the 3rd/5th harmonics cancellation. To reduce the power consumption, the multi-phase signals for the HREC are generated by DLL at low frequency. The TX is designed in 65-nm CMOS process with a core area of 0.05 mm2, achieving the 3rd/5th harmonics rejection > 40 dBc/ 52 dBc, respectively. It consumes a DC power of 1.1 mW from a 1 V-supply while delivering a -16 dBm output power.