For implementing chips with sub-7nm technology, it becomes much hard to access I/O pins on the highly dense standard cells to make physical routes for nets connecting cells. To improve the pin accessibility, in this work, we propose a cell layout optimization technique, which is able to trade fins with MOL (middle-of-line) in-cell routing resource, thus providing more M1 (metal-1) resource available to be used for I/O pin pattern extension, thereby improving the cell pin accessibility. Through experiments, it is confirmed that by making use of fin depopulation, we can consistently reduce the total wire length due to easier pin accessibility of our cells while incurring fewer number of routing failures.