Network-on-Chip (NoC) is a communication paradigm that has increased in popularity as a solution for intra-chip communication in complex System-on-Chip (SoC) designs, as it avoids complex interconnects. The functional verification of the NoC is a crucial step in the design life-cycle of a NoC based SoC, as it directly impacts the SoC behavior and latency. Automation of the NoC functional verification process could greatly improve the time-to-market of such complex SoC designs. One such approach to automation is the use of Genetic Algorithm to generate NoC traffic such that it achieves maximum functional coverage in less simulation time.