The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor’s response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into consideration. This paper proposes an optimized data driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A, simulated and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further analyse and introduce a new concept of “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.