Optimization of silicon height, width, and overall footprint for lower power consumption, enhanced integration density, and higher performance in gate all-around (GAA) 3D stacked nanosheet devices is discussed in this paper. Electrical characteristics of vertically stacked nanosheet devices are compared with FinFETs under equal silicon area and ON current constraints. Assuming a tight vertical silicon sheet pitch of 5nm, test circuits with the vertically stacked nanowires provide comparable speed with active mode energy consumption, silicon area, and idle mode leakage power consumption savings of up to 40.24%, 21.81%, and 63.48%, respectively, as compared to FinFETs in a 5nm CMOS technology