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![Matheus Pontes Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/1151.png?h=2c4e73f8&itok=1J9QuWVM)
Display Name
Matheus Pontes
- Affiliation
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AffiliationUniversidade Federal de Pelotas - UFPEL
- Country
Abstract
The aggressive technology scaling has significantly affected the circuit reliability.Techniques have been explored to mitigate the scaling effects and guarantee reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit.