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Video s3
    Details
    Presenter(s)
    Matheus Pontes Headshot
    Display Name
    Matheus Pontes
    Affiliation
    Affiliation
    Universidade Federal de Pelotas - UFPEL
    Country
    Author(s)
    Display Name
    Matheus Pontes
    Affiliation
    Affiliation
    Universidade Federal de Pelotas - UFPEL
    Affiliation
    Affiliation
    Universidade Federal de Pelotas
    Affiliation
    Affiliation
    Universidade Federal do Rio Grande
    Display Name
    Leomar Rosa Jr.
    Affiliation
    Affiliation
    Universidade Federal de Pelotas
    Affiliation
    Affiliation
    Universidade Federal do Rio Grande do Sul - UFRGS
    Abstract

    The aggressive technology scaling has significantly affected the circuit reliability.Techniques have been explored to mitigate the scaling effects and guarantee reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit.

    Slides
    • The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis (application/pdf)