The newly discovered Memristor device is finding its way in today's circuit design. It is believed that processing and saving data in Memristors improve chip performance, and they might become an alternative solution for the CMOS technology scaling problem. This work presents the design of 4-bit Up-Down counter utilizing the hybrid Memristor-CMOS platform. The simulation results have proven design and functionality of the proposed circuit. The proposed design employs fewer numbers of transistors than pure CMOS based design. Therefore, the design has a smaller layout area and shows a reasonable reduction in power consumption and delay. While other Up-Down counter designs which are relied on the pure Memristive method “IMPLY” reported less area, however, our design overcomes the issues of delay and complexity produced by the lengthy operational steps associated with IMPLY based design.