The SHA-256 algorithm is widely used in the field of security. In this paper, we propose a rescheduling method for the SHA-256 round computation. Based on the proposed rescheduling, we propose a design for SHA-256, in which the critical path is reduced. Our design is implemented on the Xilinx Virtex-4 FPGA. It achieves the throughput of 1984 Mbps with the area of 979 slices. Compared with other designs on FPGA, our design shows a better performance in terms of the throughput.