This paper presents a hardware architecture for a post-quantum key exchange protocol, named supersingular isogeny Diffie–Hellman (SIDH). The proposed hardware employs residue number system (RNS) and is optimized to reduce the latency of Fp2 multiplication and RNS Montgomery reduction, which are major time-consuming procedures in SIDH. The performance of the proposed hardware is validated and evaluated through an experimental implementation on Xilinx Kintex7 Ultrascale+. As a result, we confirm that the proposed hardware can perform an SIDH computation 34% faster than the state-of-the-art existing one on the same device at a resource overhead.