This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement techniques divides the control loops dynamics into three phases consisting of the current regulation circuits (CRC), derivative path control circuits, and the hybrid passive-active frequency compensation (PAFC) circuit. The LDO is designed in a TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm^2 active area. The quiescent current is 380 uA at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6 $mu$s, 4.5 us, and 9.8 us, respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.