Long BCH codes are broadly used in communications and storage. This paper first proposes a new state-transition-based parallel design of long BCH encoders that allows the input to be added to any tap of the linear feedback shift register without sacrificing the throughput. Then the involved matrices are analyzed to identify the optimal input tap leading to minimal complexity. Besides, hardware units sharing for matrix multiplications is enabled through analyzing the timing of the encoder. For a 32-parallel (8191, 7684) BCH encoder, our design achieves 57% higher efficiency in terms of throughput/area ratio compared to the best prior design.