Power gating (PG) is an important technique of energy-efficient LSIs to realize additional applications for Internet-of-Things devices in the future, but it also has issues including circuit performance degradation and increased area overhead. In this paper, we designed a new PG switch array with its control unit based on an optimum switch-timing control scheme to obtain a high-performance/low-area implementation. According to the simulation results based on 45nm CMOS under HSPICE, the maximum inrush current is reduced by up to 95.6% and the minimum wake-up-time is only 0.22ns.