High-resolution analog signal conditioning or processing circuit requires careful design of building blocks to minimize any circuit non-idealities due to the manufacturing process and operating conditions. In this paper, we present a highly precise analog subtractor circuit with several background calibration techniques. This circuit is designed and can be further developed for the capacitive-based successive subtraction ADC circuit. Our proposed calibration method is based on a capacitive-array of 15 unary-weighted unit capacitors, which compensates errors due to the amplifier’s voltage offset and capacitors’ mismatches and parasitic capacitance. The circuit is implemented using 45nm CMOS technology, and the power consumption is 82.8μW. It operates at a frequency of 166.7kHz, corresponding to 6μs per operation. With our calibration method, we have reduced an average percentage error from 3.99% to 0.457% across the entire dynamic range, and with the worst-case error of 700μV.