This work presents a linearized Ka-band heterodyne receiver for millimeter-wave phased-array systems with high linearity requirement. A folded class-AB inductive peaking mixer and a two-stage magnetic self-cancellation based load-pull interstage matching Intermediate-frequency (IF) amplifier are proposed to improve the linearity of input and output 1-dB compression point, respectively. The proposed receiver is implemented in 65 nm CMOS technology and its core area is 0.7 mm2. The measured input 1-dB compression point (IP1dB) is -10.9 dBm and the output 1-dB compression point (OP1dB) is 7.1 dBm, with noise figure (NF) of 10.1 dB at center frequency. To the best knowledge of the authors, the proposed RX achieves the highest IP1dB and OP1dB among all the listed publications in silicon technology. The power consumption of the receiver including LO path is 119mW.