Increasing the throughput of nonbinary low-density parity-check (NB-LDPC) decoders is carrying out a big challenge. In this paper, by taking the features of nonbinary quasi-cyclic LDPC codes, we propose a decoding schedule named early layered decoding schedule. The proposed method can eliminate the idle time after each layered decoding process introduced by the pipeline stages in the decoder design, and increase the throughput of the decoder as well. Besides, the layout results, where TSMC 90-nm CMOS technology is used, demonstrate that the proposed decoding schedule can improve throughput of the previous NB-LDPC decoders at almost the same hardware complexity. Especially, in the case of both early layer decoding schedule and early decoding termination are enabled, there is a much improvement in terms of efficiency compared with the predecessors.