This paper proposes the BLAKE-256 accelerator to achieve high performance and hardware efficiency for securing the blockchain networks. To achieve those goals, the proposed BLAKE-256 accelerator has three novel optimization techniques, including a fully unrolled datapath, a pipelined arithmetic-logic unit (ALU), and nonce generating and checking block mechanisms (NGB and NCB). Based on our experiments on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA at the system-on-chip level, the impact of proposed optimization techniques is clearly proven. Moreover, experimental results on several FPGAs show that our proposed accelerator has significantly better throughput and area efficiency than previous BLAKE-256 architectures.