All-digital basestation architectures enable superior spectral efficiency compared to hybrid solutions in massive MU-MIMO systems. However, supporting traditional all-digital baseband architectures in such systems would result in excessively high power consumption and large silicon area. The recently-proposed finite-alphabet equalization addresses these issues by using equalization matrices that contain low-resolution entries to reduce hardware power and complexity. In this paper, we explore two different finite-alphabet equalization hardware implementations that tightly integrate memory and processing: (i) a parallel array of multiply-accumulate units and (ii) a bit-serial processing-in-memory architecture. Our VLSI implementation results show that these architectures trade-off area versus power consumption.