This paper explores the implications of designing and implementing a high-quality interpolation filter in a low-latency digital to analog converter (DAC) context. The main finding is that the phase delay and the implementation complexity of the filter augment sub-linearly with the filter size. The implementation uses parallelized polyphase filters with special attention given to quantization. Substantial variations in the coefficient’s amplitude level between the parallelization branches made it possible to use different quantization while reducing the overall complexity. The system was implemented on System Generator for DSP (SysGen).