FPGA-based TDCs suffer from large bin width variations. This issue imposes performing a calibration process to compensate for the nonlinearity of the TDC. The most commonly used calibration technique is the Bin–by-bin calibration that can improve the DNL of the TDC up to 10 times. In this paper, we propose a new robust calibration method for asynchronous TDCs. The simulation results showed that the proposed method improves the DNL up to 100 times. These results have been confirmed by experimental measurements.