We present a high-performance and low-overhead multicast network-on-chip (NoC) architecture for hierarchical address event routing (Multicast-HiAER) suitable for large-scale reconfigurable neuromorphic systems. Each building block of this efficient NoC architecture consists of several multi-cast advanced high-performance buses (mAHB) running in parallel for high-bandwidth inter-core spike event transmission. This architecture for scalable event routing can help to implement brain-scale neural network connectivity distributed across neuromorphic processing cores, with network constraints typical of locally dense and globally sparse neuron connectivity. For a demonstration using a Xilinx Virtex Ultrascale VU37p FPGA, we have shown an 8$times$8 grid of mAHBs running at 512MHz clock performing Level-1 and Level-2 inter-core communication at top bandwidth of 420M events per second per 128k neuron node in the hierarchy. This peak absolute bandwidth supports spike event registration with sub-ms latencies under worst-case conditions of all postsynaptic destinations being off-core.