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Presenter(s)
![Daniel García-Lesta Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/21692.jpg?h=6b698b4b&itok=INDf4tdD)
Display Name
Daniel García-Lesta
- Affiliation
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AffiliationUniversidade de Santiago de Compostela
- Country
Abstract
This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128x64 (8192) processing units (PUs) with 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Postlayout simulations of the complete system working on various basic operations are shown.