Perceptron is the basic computation unit of neural network architectures. This work proposes a resource-efficient and fast hardware for perceptron and MLP network. The inner product computation unit and activation function evaluation unit is designed using Offset Binary Coding (OBC) and Co-ordinate Rotation Digital Computer (CORDIC) respectively. The proposed hardware is implemented on Field Programmable Logic Array (FPGA) and synthesized on 65 nm Application Specific Integrated Chips (ASIC). It achieved a speed-up of at least 21x as compared to software. The total area and power consumed was 0.085662 mm^2 and 2.28 mW respectively @200 MHz.