This paper proposes a new sub-element T-network to analyze resistive DACs as a cascade of these T-networks. This paper also proposes a new 3-node voltage method, a modified 2-Port analysis transformed into a 3-node voltage equation, making the analysis simpler for a wide range of generic resistive DACs. The INL of R-2R and Thermometric DACs was derived and extension to a Segmented DAC was demonstrated. Intuitive appreciation of the DAC topologies and worst case INL, DNL and the code at worst INL/DNL was presented towards the end to enable easy choice of topologies for a resistive DAC application.