This paper proposes a fully synthesizable digital low-dropout (DLDO) regulator using an automatic offset control and reuse technique implemented in a 65-nm CMOS technology. To realize the fully synthesizable DLDO design, all components of core blocks are made with standard logic cells. The proposed offset control and reuse technique is adopted to cancel the offset voltage from the logic cells automatically, to provide the adaptive equivalent thresholds for the voltage comparison window, and to speed up the dropout voltage response. Besides, the modified comparator-triggered oscillator introduces the output of the comparator to the oscillation loop to choose the optimum clock edge in the delay line to feed back, which ensures both of the fast response and enough time margin for the comparator delay at the same time. The core area of the output-capacitance-less DLDO is 0.027 mm^2. The simulated results show that a 100 mA step in load current produces a voltage drop of 140 mV with the response time of 1.2 ns. The steady-state error is less than 4 mV. The peak current efficiency is 99.9%.