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Video s3
    Details
    Presenter(s)
    Pratap Tumkur Renukaswamy Headshot
    Affiliation
    Affiliation
    IMEC
    Country
    Country
    Belgium
    Abstract

    This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low-area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measured the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), so as to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

    Slides
    • Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation (application/pdf)