Debugging SDN hardware becomes more and more difficult, and malfunctioning can occur during hardware implementation, even if a simulation-based verification passed successfully. To this end, we propose a hardware/software co-verification tool that provides verification and validation of configurable network applications. The system integrates software simulation, relying on an open-source simulator, and hardware implementation, embedding the DUT and its test interface on FPGA. It allows data exchange between the host and FPGA. Reported experiments have been conducted on the NetFPGA-SUME and CocoTB cooperating with GHDL. Cycle-accurate data capture is achieved with less than 2% of resources occupied.