Decision Tree (DT) algorithms perform classification of data according to decision criteria obtained during training which results in high computational complexity and latency. In this paper, a Hybrid DT (HDT) is proposed which reduces training complexity and achieves 8x speed-up as compared to conventional DT. The critical path of proposed HDT hardware enables the FPGA to operate at a maximum frequency of 125 MHz. Simulation results show that the proposed hardware achieves $1000times$ speed-up as compared to software-based realisation and $60times$ speed-up as compared to existing FPGA training accelerator.