Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit CT delta-sigma modulator by adapting an FIR filter in the feedback DAC. However, when applying this to CT incremental delta-sigma modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental delta-sigma conversion cycle, which limits the dynamic range of the modulator. This paper describes the challenges that come with acquiring an FIR DAC in an incremental delta-sigma modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental delta-sigma modulator, which is very beneficial to promote high speed/resolution designs.