High-speed time-interleaved analog-to-digital converters (TI-ADCs) are sensitive to timing skew mismatch. Autocorrelation-based background timing skew calibration techniques require small hardware overhead as they rely on the TI-ADC input signal for calibration. However, such techniques suffer from a very long convergence time. This paper proposes a new correlation-based technique that boosts convergence speed by orders of magnitude compared to existing autocorrelation-based techniques. The technique uses a digital window detector and calculates the signal correlation funnction around zero-crossings only. Practical design considerations including thermal noise, clock jitter, quantization and offset mismatch are discussed. Behavioral simulation results for two TI-ADCs with different speeds, resolutions and interleaving factors are presented.