The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.