In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (E-D) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.