This paper presents a new energy efficient Fast-Fourier Transform (FFT) architecture for real-valued applications. The proposed architecture decimates the FFT in time domain which allows to avoid the use of the costly complex FFT. This leads to the reduction of the required memory by a factor of 2 while processing two inputs in parallel, thus doubling the throughput and improving the energy efficiency compared to the existing real-valued FFT designs. Furthermore, the output frequencies are computed at their natural order by using a novel memory management technique, without requiring any reordering circuit unlike existing works. In summary for a N point FFT the proposed architecture leads to an increased N / 2 latency requiring N – 2 memory cells, 8logN – 8 real adders and 3logN – 4 real multipliers. Our results show we can achieve up to 46.86% energy savings when compared with existing real-valued FFT architectures.