Recently, Stochastic Computing has sparked interest in Bayesian inference resolution for its promising efficiency in area and power consumption. Still, in a sequential architecture, most of the energy cost is due to the long computation time required for achieving a satisfying accuracy. In this paper, we propose a multi-rail architecture based on a Shift Register Isolator and permutations in order to reduce the computation time and thus the energy consumption, without a significant increase in area. Indeed, we are able to reduce the energy consumption by up to 73% in return for an area overhead of 24%, while maintaining the computation accuracy.