Parallelism and pipelining are widely used to improve the performance and throughput of systems. However, its effect on energy consumption needs to be studied. In this paper the alteration in energy consumption that results from using parallel architecture is studied over LWC algorithms from NIST standardization process. Ten algorithms are currently in the final round of the standardization process. Two algorithms out of the ten final round candidates can be parallelized which are Elephant and ISAP algorithms. For these algorithms, both iterative looping and parallel architectures are designed and synthesized over ASIC GF22nm technology. Then both architectures are compared in terms of area, throughput and energy. Results showed an enhancement in energy efficiency up to 49% and 28% and throughput improvement reaches up to 96% and 45% in Elephant and ISAP, respectively.