Power, area, and delay trade-offs occupy a vital role in early pre-fabrication design decisions for various System-on-Chip and intermittently powered devices. The asymmetry between read/write energy consumption and active/standby duty cycles are used herein to facilitate trade-offs between use of embedded 6T-SRAM versus embedded MRAM-based on Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) 2T-1R single bit cell structure. A model is developed and validated to estimate power in hybrid CMOS/MTJ technology with a coefficient of determination R^2>0.95. The approach employs three new metrics: Mean Standby Duration (MSD), Mean Active Duration (MAD), and Power Dissipation Scaling Ratio (PDSR).