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Video s3
    Details
    Presenter(s)
    Bappaditya Dey Headshot
    Display Name
    Bappaditya Dey
    Affiliation
    Affiliation
    University of Louisiana at Lafayette
    Country
    Country
    United States
    Author(s)
    Display Name
    Kasem Khalil
    Affiliation
    Affiliation
    University of Louisiana at Lafayette
    Display Name
    Bappaditya Dey
    Affiliation
    Affiliation
    University of Louisiana at Lafayette
    Affiliation
    Affiliation
    California State University, Bakersfield
    Display Name
    Ashok Kumar
    Affiliation
    Affiliation
    University of Louisiana at Lafayette
    Display Name
    Magdy Bayoumi
    Affiliation
    Affiliation
    University of Louisiana at Lafayette
    Abstract

    Neural networks have been used in several domains and applications in our life. One of the main challenges is the hardware implementation of neural networks. The hardware design is fixed in the number of nodes and layers that make the network is applied to specific applications. This paper presents a reconfigurable neural network where the number of layers and nodes can be changed according to the applications. The proposed method is based on Network-on-Chip (NoC) which is used for routing data between layers and nodes. Each router, in NoC, is connected to m nodes that can represent a part or complete layer. According to the reconfiguration, the number of routers can be selected to present the number of layers, and the number of nodes per layer is decided by the needed nodes in each router. The proposed method is implemented on FPGA Altera 10 GX, and it achieves an accuracy of 97% for using the MNIST dataset. The throughput and delay of the proposed method have efficient results compared to the traditional method.

    Slides
    • An Efficient Reconfigurable Neural Network on Chip (application/pdf)