Generalized integrated interleaved (GII) codes are essential to next-generation communications and distributed storage. They achieve hyper-speed decoding with excellent error-correction capability. This paper proposes novel algorithmic reformulations and architectural transformations to substantially reduce the complexity of GII decoders. For an example GII code, the proposed decoder achieves more than seven orders of magnitude improvement in error-correcting performance with less than 30% area overhead compared to a Reed-Solomon decoder. With a critical path of seven XOR gates, the proposed decoder can easily achieve more than 40 GByte/s throughput.