Convolutional neural networks (CNNs) have been evolving with tremendous success. The conventional hardware, however, is facing difficulty in realizing real-time and energy-efficient operations on CNN. To efficiently operate CNNs on hardware, researchers are actively studying processing-in-memory (PIM) with resistive random-access memory (ReRAM). Digital PIM is particularly attractive since analog designs struggle with undesirable device properties and additionally required circuits. However, the massive area originated from digital PIM is a hindrance to its applications. Thus, this work presents a three-dimensional (3D) ReRAM convolution logic processor design to tackle the limitation of digital PIM. At the hardware level, we leverage 3D ReRAM for area efficiency; on the other hand, the design simplicity is accomplished by exploiting binarized weight networks (BWNs) at the algorithm level. Specifically, our 3D ReRAM processor computes convolutions of BWNs based on two proposed schemes to maximize resource efficiency. Consequently, the proposed design achieves 3.7X to 5.7X and 5X to 42.5X area- and time-saving according to the bit precision in comparison to the original digital PIM.