This paper presents a novel design method for asynchronous control logic targeting successive approximation register (SAR) analogue-to-digital converters (ADCs). This work is based on modelling the control logic for SAR ADCs using signal transition graphs (STGs). Different from conventional synchronous controllers, the proposed method results in asynchronous controllers driven by the causality of signals rather than relying on clocks to control the conversion. This work results in a formal, model-based asynchronous design flow for SAR ADC control, which is shown to produce resulting circuits of similar speeds but more than an order of magnitude of power efficiency improvements.