this paper proposes a new dual-mode low-dropout linear regulator without external capacitors, which mainly includes three error amplifiers, an offset voltage generator, a mode decision circuit and a pre-biasing load transient enhancement circuit. The chip uses a 28nm CMOS process to verify the advantages brought by the architecture of this paper. The measurement results show that the output voltage has almost negligible undershoot and overshoot (both less than 5mV) during mode transition. In load transient response, due to the use of pre-charge technique, the output voltage undershoot and overshoot are reduced by 45.2% and 36%, respectively. Finally, this architecture achieves FoM to be close to 1fs.