Details
Presenter(s)
![Rizwan Shaik Peerla Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/20541.jpg?h=c044e3d4&itok=mmQOfzBd)
Display Name
Rizwan Shaik Peerla
- Affiliation
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AffiliationIndian Institute of Technology, Hyderabad
- Country
Abstract
This paper presents a low phase noise (PN), dual voltage controlled oscillator (VCO), integer-N phase locked loop (PLL) for navigation receiver operating atL5andSbands. The PLL incorporates a proposed extended range multi modulus divider (MMD) in the feedback path. Fabricated in UMC 65nm CMOS, the PLL is powered at 1.2V supply consuming 12mW power. The PLL achieves a PN of −122 dBc/Hz and −120 dBc/Hz at 1M Hz offset forL5-band and S-band respectively.